Advanced Mos Device Engineering Utilizing a Technology Cad Framework

A TCAD framework has been developed which integrates process, device and interconnect simulation tools, a simulation database, a TCAD shell and a graphical user interface into a homogeneous environment. In this paper, the utilization of this framework for the development of advanced devices and the impact on computer-aided MOS device engineering will be demonstrated using several examples. The use of CAD tools for analysis and prediction of IC technology is generally a substitute for experiments in order to save time, efforts and money, and to provide additional insight into process and device physics. We have integrated the required simulation tools into the technology CAD (TCAD) framework VISTA [1), featuring a common format for data exchange [2) and a TCAD shell [4), which provides for easy combination of all the different functional units through a of a powerful LISP-based command and extension language [3) for defining and solving high-level engineering tasks. Short shell programs couple process simulation with several runs of a MOS device simulator [5) and postprocessing tools to automate the computation of I-V characteristics and to display them immediately. Taking advantage of the inherent parallelism of data independence, the device simulator is run simultaneously on several machines, making use of remote compute servers or workstation clusters. The identification of the impact of variations in the fabrication process on device performance is a typical TCAD application. The effect of varying the spacer width, resulting from a not-so-easy-to-control back-etch process during spacer formation, on the device behavior in the strong inversion regime has been investigated for a high voltage p-channel MOSFET (Fig. 1). For technology optimization, process and device simulation are coupled with an optimizer forming a closed loop. Extensive profile characterization is necessary to verify that all other specifications besides the optimized ones a.re met for the improved device. A well-known example is the bulk current minimization obtained by varying the LDD implant dose of an n-channel MOS transistor. The result is the lb/ Id versus LDD implant dose diagram in Fig. 2. The improvement of the punch-through immunity of a p-channel device has been subject of another investigation, also carried out by utilizing our VISTA system. This goal has been achieved by raising the well doping concentration and simultaneously adjusting the threshold adjust implant dose under the constraint of an unchanged threshold voltage. 1 to appear in: Proc. Third International Conference on Solid State and Integrated Circuit Technology, ICSICT '92, Oct. 18-24, 1992, Beijing, China